Professor H.S. Jatana has visited MNIT Jaipur from 12 th to 14 th November, 2024, as an adjunct faculty and enlighten our Undergarduate and masters students with his great expertise in VLSI chip design and layout design. He received his engineering education BTech (hons) from BITS Pilani and had a brief stint at CMC Delhi as Software engineer wherein he worked on Railway Computerization Project, and later joined SCL in the CMOS division. He worked at Rockwell Semiconductor, California, USA where he was involved in design of R65 series of devices. He has worked in different areas of CMOS and has vast experience on CMOS design, Device testing /, characterization, Test program development on ATE, Silicon debugging, and process Integration / porting over few technology nodes; starting from 5µm to sub-micron nodes. He also worked at AMS Austria for ten months on deputation for porting of SCL’s CMOS processes at their foundry.